Conventional digital integrated circuits comprise complex combinational networks for performing logical operations on data, and memory elements interconnected with the combinational networks to provide memory functions essential to the operation of the combinational networks. Such integrated circuits are difficult to test due to the complexity of their operation.
Modern digital integrated circuit designers incorporate test features in digital integrated circuits at the design stage to ensure that such circuits are testable. In one design technique, known as Level Sensitive Scan Design (LSSD), designers partition circuits into combinational networks and scannable memory elements, usually flip-flops. The flip-flops are made reconfigurable from their operating configuration (in which they are connected to the combinational networks of the circuit as required to support normal operation of the circuit) to a scan configuration in which they are decoupled from the combinational networks and connected in series to form one or more shift registers known as a "scan chains".
The scan configuration is used during testing of the circuit to shift a known test stimulus pattern into the scan chains. The flip-flops are then put into the operating configuration for at least one clock cycle so that the combinational networks perform logical operations on some of the data making up the test stimulus pattern and alter the data stored in some of the flip-flops. The flip-flops are then returned to the scan configuration to shift the altered data out of the scan chains as a test response pattern. The test response pattern is compared with a calculated test response pattern or with a test response pattern obtained from a circuit which is known to be functioning properly to determine whether the circuit under test is functioning properly.
U.S. Pat. No. 4,503,537 discloses apparatus for testing a multichip module in which a single random pattern generator supplies random test stimulus patterns in parallel to respective scan chains of digital integrated circuits (or "chips") making up the multichip module. A single signature register receives test response patterns in parallel from the respective scan chains of the integrated circuits for evaluation. (U.S. Pat. No. 4,503,537 issued Mar. 5, 1985 in the name of W.H. McAnney and is entitled "Parallel Path Self-Testing System".)
In the test apparatus disclosed in U.S. Pat. No. 4,503,537, the respective scan chains of the individual integrated circuits are all clocked at the same rate. This clock rate is limited by the longest propagation delay between scannable memory elements through the combinational networks of all integrated circuits making up the multichip module. If a higher clock rate were used, one or more of the combinational networks would not have adequate time to operate on the test stimulus pattern and the test response pattern would not accurately represent the operation of the combinational networks on the test stimulus pattern.
Where there is a distribution of propagation delays through the combinational networks between scannable memory elements, the apparatus of U.S. Pat. No. 4,503,537 tests some combinational networks at a clock rate which is lower than necessary, so that the time required to complete testing of those combinational networks is unduly long. Moreover, the clock rate for testing will generally be lower than the clock rate used during normal operation for at least some of the memory elements, so the test results may not accurately represent the operation of those memory elements and their associated combinational networks at normal operating speed. In particular, certain faults resulting from excessive propagation delays during normal circuit operation may go undetected.